VLSI Symposia to be held in June 2015 in Kyoto, Japan publishes its advance program. Few notable papers on image sensors:
VLSI Circuit Symposium has 5 image sensor papers. Probably, the most interesting one comes from Olympus:
A 3D Stacked CMOS Image Sensor with 16Mpixel Global-Shutter Mode and 2Mpixel 10000fps Mode Using 4 Million Interconnections
T. Kondo, Y. Takemoto, K. Kobayashi, M. Tsukimura, N. Takazawa, H. Kato, S. Suzuki, J. Aoki, H. Saito, Y. Gomi, S. Matsuda and Y. Tadaki, Olympus, Japan
A 16Mpixel 3D stacked CMOS image sensor with pixel level interconnections using 4,008,960 micro bumps at a 7.6μm pitch, which set no layout restriction and causes no harm to sensor characteristics, was developed to achieve both a 16Mpixel global-shutter mode with a -180dB PLS and 2Mpixel 10000fps high speed image capturing mode.
The second most interesting paper is one from Tohoku University:
A Linear Response Single Exposure CMOS Image Sensor with 0.5e- Readout Noise and 76ke- Full Well Capacity
S. Wakashima, F. Kusuhara, R. Kuroda and S. Sugawa, Tohoku Univ., Japan
A linear response single exposure CMOS image sensor approaching to the photon countable sensitivity and a high full well capacity is developed using lateral overflow integration capacitor architecture with dual gain column amplifiers, small floating diffusion capacitance and low noise in-pixel source follower signal readout technologies. The fabricated 5.5 um pitch 360H x 1680V pixel prototype image sensor exhibited 240 μV/e- conversion gain with 76 ke- FWC resulting in 0.5 erms readout noise and 104 dB dynamic range under room temperature operation.
Image Sensor/Digital Logic 3D Stacked Module Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
M. Ikebe*, D. Uchida*, Y. Take**, M. Someya*, S. Chikuda*, K. Matsuyama*, T. Asai*, T. Kuroda** and M. Motomura*, *Hokkaido Univ. and **Keio Univ., Japan
This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming TDC used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.
A 0.66e-rms Temporal-Readout-Noise 3D-Stacked CMOS Image Sensor with Conditional Correlated Multiple Sampling (CCMS) Technique
S.-F. Yeh, K.-Y. Chou, H.-Y. Tu, C. Y.-P. Chao and F.-L. Hsueh, TSMC, Taiwan
A conditional correlated multiple sampling (CCMS) technique for low noise CMOS image sensor (CIS) is proposed to reduce noise and address low frame rate issue caused by the conventional correlated multiple sampling (CMS) technique. An 8Mpixel 3D-stacked CIS with 1.1um pixel pitch is designed and verified. Measurement results show this technique can achieve 0.66erms at 36.1 kHz A/D sampling rate per pixel with analog gain at 16 and 5-times multiple sampling. The resulting DNL is within -0.49/+0.45LSB.
A 0.4V Self-Powered CMOS Imager with 140dB Dynamic Range and Energy Harvesting
A. Y.-C. Chiou and C.-C. Hsieh, National Tsing Hua Univ., Taiwan
This PWM imager operates at a lowest reported supply 0.4V with a 0.42x smaller pixel size, 1.5x larger fill factor, 0.58 smaller random noise, and 3x better iFoM than previous work. With proposed dual-exposure extended-counting (DEEC) scheme, the prototype achieves a high dynamic range of 140dB with a 58dB boost. Optical energy harvesting (OEH) design is implemented to generate 60.3pW per lux per mm2 and 1.28x higher efficient than current design. A self-powered imager is demonstrated with 15fps under 100klux.
VLSI Technology Symposium has one image sensor paper:
Energy Efficient 1-Transistor Active Pixel Sensor (APS) with FD SOI Tunnel FET
N. Dagtekin and A. M. Ionescu, EPFL, Switzerland
This paper presents the first energy efficient highly compact concept of active pixel sensor built with a single partially-gated tunnel FET (TFET). Experimental results show that the transistor characteristics of the investigated TFETs are nonlinearly modulated by optical excitation and an optical gain is reported for the first time. A memory effect is observed and exploited when the back-gate is used as a secondary gate to control charge storing mechanism in the body, similarly to back gate illuminated photodiode pixels. Compared to CMOS, 1T-TFET pixels offer high sensitivity (detection limit < 2pW/μm2 in visible light), low power operation, improved temperature stability and high compactness (1T architecture with pixel size of ~10x1μm2 in this work).
VLSI Circuit Symposium has 5 image sensor papers. Probably, the most interesting one comes from Olympus:
A 3D Stacked CMOS Image Sensor with 16Mpixel Global-Shutter Mode and 2Mpixel 10000fps Mode Using 4 Million Interconnections
T. Kondo, Y. Takemoto, K. Kobayashi, M. Tsukimura, N. Takazawa, H. Kato, S. Suzuki, J. Aoki, H. Saito, Y. Gomi, S. Matsuda and Y. Tadaki, Olympus, Japan
A 16Mpixel 3D stacked CMOS image sensor with pixel level interconnections using 4,008,960 micro bumps at a 7.6μm pitch, which set no layout restriction and causes no harm to sensor characteristics, was developed to achieve both a 16Mpixel global-shutter mode with a -180dB PLS and 2Mpixel 10000fps high speed image capturing mode.
The second most interesting paper is one from Tohoku University:
A Linear Response Single Exposure CMOS Image Sensor with 0.5e- Readout Noise and 76ke- Full Well Capacity
S. Wakashima, F. Kusuhara, R. Kuroda and S. Sugawa, Tohoku Univ., Japan
A linear response single exposure CMOS image sensor approaching to the photon countable sensitivity and a high full well capacity is developed using lateral overflow integration capacitor architecture with dual gain column amplifiers, small floating diffusion capacitance and low noise in-pixel source follower signal readout technologies. The fabricated 5.5 um pitch 360H x 1680V pixel prototype image sensor exhibited 240 μV/e- conversion gain with 76 ke- FWC resulting in 0.5 erms readout noise and 104 dB dynamic range under room temperature operation.
Image Sensor/Digital Logic 3D Stacked Module Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
M. Ikebe*, D. Uchida*, Y. Take**, M. Someya*, S. Chikuda*, K. Matsuyama*, T. Asai*, T. Kuroda** and M. Motomura*, *Hokkaido Univ. and **Keio Univ., Japan
This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming TDC used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.
A 0.66e-rms Temporal-Readout-Noise 3D-Stacked CMOS Image Sensor with Conditional Correlated Multiple Sampling (CCMS) Technique
S.-F. Yeh, K.-Y. Chou, H.-Y. Tu, C. Y.-P. Chao and F.-L. Hsueh, TSMC, Taiwan
A conditional correlated multiple sampling (CCMS) technique for low noise CMOS image sensor (CIS) is proposed to reduce noise and address low frame rate issue caused by the conventional correlated multiple sampling (CMS) technique. An 8Mpixel 3D-stacked CIS with 1.1um pixel pitch is designed and verified. Measurement results show this technique can achieve 0.66erms at 36.1 kHz A/D sampling rate per pixel with analog gain at 16 and 5-times multiple sampling. The resulting DNL is within -0.49/+0.45LSB.
A 0.4V Self-Powered CMOS Imager with 140dB Dynamic Range and Energy Harvesting
A. Y.-C. Chiou and C.-C. Hsieh, National Tsing Hua Univ., Taiwan
This PWM imager operates at a lowest reported supply 0.4V with a 0.42x smaller pixel size, 1.5x larger fill factor, 0.58 smaller random noise, and 3x better iFoM than previous work. With proposed dual-exposure extended-counting (DEEC) scheme, the prototype achieves a high dynamic range of 140dB with a 58dB boost. Optical energy harvesting (OEH) design is implemented to generate 60.3pW per lux per mm2 and 1.28x higher efficient than current design. A self-powered imager is demonstrated with 15fps under 100klux.
VLSI Technology Symposium has one image sensor paper:
Energy Efficient 1-Transistor Active Pixel Sensor (APS) with FD SOI Tunnel FET
N. Dagtekin and A. M. Ionescu, EPFL, Switzerland
This paper presents the first energy efficient highly compact concept of active pixel sensor built with a single partially-gated tunnel FET (TFET). Experimental results show that the transistor characteristics of the investigated TFETs are nonlinearly modulated by optical excitation and an optical gain is reported for the first time. A memory effect is observed and exploited when the back-gate is used as a secondary gate to control charge storing mechanism in the body, similarly to back gate illuminated photodiode pixels. Compared to CMOS, 1T-TFET pixels offer high sensitivity (detection limit < 2pW/μm2 in visible light), low power operation, improved temperature stability and high compactness (1T architecture with pixel size of ~10x1μm2 in this work).
Image Sensors at 2015 VLSI Symposia
![Image Sensors at 2015 VLSI Symposia]()
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April 21, 2015
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