EV Group (EVG) joins the 3D integration consortium of IRT Nanoelec headed by CEA-Leti and includes STMicro and Mentor Graphics to develop advanced 3D wafer-to-wafer bonding technologies. SET also joined recently the consortium.
Séverine Chéramy, director of the 3D integration program of IRT Nanoelec, said the consortium expects to achieve an interconnection pitch of about 1µm.
"Wafer-to-wafer stacking using direct Cu-to-Cu bonding is key for advanced 3D technologies, specifically for imaging application and 3D partitioning," Chéramy said. "EVG's knowledge on bonding will leverage the process expertise of the original members. The participation of EVG in the consortium will create new opportunities and optimized and cost-effective solutions for 3D IC devices."
Séverine Chéramy, director of the 3D integration program of IRT Nanoelec, said the consortium expects to achieve an interconnection pitch of about 1µm.
"Wafer-to-wafer stacking using direct Cu-to-Cu bonding is key for advanced 3D technologies, specifically for imaging application and 3D partitioning," Chéramy said. "EVG's knowledge on bonding will leverage the process expertise of the original members. The participation of EVG in the consortium will create new opportunities and optimized and cost-effective solutions for 3D IC devices."
EVG Joins European Wafer Stacking Program
![EVG Joins European Wafer Stacking Program]()
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February 05, 2016
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