EETimes: While MIPI M-PHY is still struggling to be adopted in mobile cameras, MIPI comes up with a multi-level signalling scheme in its newest C-PHY standard proposal. "C-PHY uses a 3-pin architecture and an embedded clock. Each of the pin trios represents one lane with up to three lanes supported for a total of 9 pins. It also uses a new encoding scheme to increase the number of bits transmitted to approximately 2.28 bits per symbol. The projected data rate is 2.5 Gsymbols/s for an effective data rate of about 5.7 Gbits/s.
A further C-PHY nuance is that the signal is transmitted single-ended, but received as a differential signal. Clock is recovered from the earliest edge of the symbol transition. A delay circuit with negative hold times is used to sample data, an approach that is potentially more resistant to noise and jitter."
A further C-PHY nuance is that the signal is transmitted single-ended, but received as a differential signal. Clock is recovered from the earliest edge of the symbol transition. A delay circuit with negative hold times is used to sample data, an approach that is potentially more resistant to noise and jitter."
MIPI C-PHY Offers Higher Speeds, Better Robustness
Reviewed by MCH
on
September 02, 2014
Rating:
Reviewed by MCH
on
September 02, 2014
Rating:
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