e2v applies for a patent extending its EMCCD technology to the realm of CMOS sensors: "Electron multiplication image sensor and corresponding method" by Frédéric Mayer (France). Fig. 1 of the US20110303822 application shows a prior art 4T pixel having a pinned photodiode PHD:
e2v proposes to split the PHD into two with the "accelerating gate" GA in between, as on Fig. 2. By applying multiple voltage pulses on GA the electrons can be moved in and out of it, as shown on Fig. 3.
"The electron multiplication takes place during the charge integration and in the photodiode itself in the sense that the electrons (photogenerated or resulting already from the impacts of carriers with atoms) are accelerated in turn from the photodiode towards the accelerating gate and from the accelerating gate towards the photodiode. During these movements, impacts with atoms of the semiconductor layer of the photodiode region or of the region located beneath the accelerating gate make other electrons in the valence band pass into the conduction band. These electrons lose energy during these impacts but they are again accelerated by the electric field that is present.
The number of alternations in potential applied to the accelerating gate defines the overall multiplication coefficient obtained at the end of an integration period T, i.e. between two successive pulses for transferring charge from the photodiode to the charge storage region."
Fig. 4 shows one of the possible pixel layouts with GA located in the middle of PHD.
Update: As said in comments, in 2009 Sanyo published a different idea of electron multiplying CMOS pixel. The idea is shown on the figure below:
Update #2: As EF said in comments, Sanyo presented its electron multiplying sensor at ISSCC 2009 (paper, presentation). The pixel structure and the gain non-uniformity are taken from the presentation slides:
e2v proposes to split the PHD into two with the "accelerating gate" GA in between, as on Fig. 2. By applying multiple voltage pulses on GA the electrons can be moved in and out of it, as shown on Fig. 3.
"The electron multiplication takes place during the charge integration and in the photodiode itself in the sense that the electrons (photogenerated or resulting already from the impacts of carriers with atoms) are accelerated in turn from the photodiode towards the accelerating gate and from the accelerating gate towards the photodiode. During these movements, impacts with atoms of the semiconductor layer of the photodiode region or of the region located beneath the accelerating gate make other electrons in the valence band pass into the conduction band. These electrons lose energy during these impacts but they are again accelerated by the electric field that is present.
The number of alternations in potential applied to the accelerating gate defines the overall multiplication coefficient obtained at the end of an integration period T, i.e. between two successive pulses for transferring charge from the photodiode to the charge storage region."
Fig. 4 shows one of the possible pixel layouts with GA located in the middle of PHD.
Update: As said in comments, in 2009 Sanyo published a different idea of electron multiplying CMOS pixel. The idea is shown on the figure below:
Update #2: As EF said in comments, Sanyo presented its electron multiplying sensor at ISSCC 2009 (paper, presentation). The pixel structure and the gain non-uniformity are taken from the presentation slides:
e2v Applies for Electron Multiplying CMOS Sensor
Reviewed by MCH
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December 22, 2011
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Reviewed by MCH
on
December 22, 2011
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