As BD pointed in comments, Caeleste publications page has been updated to include the latest CNES Workshop 2011 presentations. The most interesting one is "A 0.5 noise electrons CMOS pixel" by Bart Dierickx, Nayera Ahmed, and Benoit Dupont. The presentation explains the 1/f and RTS noise reduction principle by cycling the pMOSFET between accumulation and inversion:
150 inversion-accumulation cycles are averaged to reduce pixel noise down to 0.5e level:
The result was measured on the technology demonstrator based on 100um standalone test structure, ~7μm MOSFET area, pixel is used in CTIA mode with >1000μV/e- conversion gain:
Another new CNES Caeleste presentation is "High QE, Thinned Backside-Illuminated, 3e- RoN, Fast 700fps, 1760×1760 Pixels Wave-Front Sensor Imager with Highly Parallel Readout."
150 inversion-accumulation cycles are averaged to reduce pixel noise down to 0.5e level:
The result was measured on the technology demonstrator based on 100um standalone test structure, ~7μm MOSFET area, pixel is used in CTIA mode with >1000μV/e- conversion gain:
Another new CNES Caeleste presentation is "High QE, Thinned Backside-Illuminated, 3e- RoN, Fast 700fps, 1760×1760 Pixels Wave-Front Sensor Imager with Highly Parallel Readout."
Caeleste Presents its 0.5e- Noise Pixel and More
Reviewed by MCH
on
December 13, 2011
Rating:
Reviewed by MCH
on
December 13, 2011
Rating:
No comments: