The new version of ISSCC 2011 Advance Program includes abstracts. Some of them are quoted below:
A 1.32pw/frame∙pixel 1.2v CMOS Energy-Harvesting and Imaging (EHI) APS Imager
S. U. Ay
University of Idaho, Moscow, ID
A CMOS energy-harvesting and imaging (EHI) APS imager capable of 7.4fps video capture and 3.5μW power generation is designed, fabricated, and tested in 0.5μm CMOS. It has a 54×50 array of 21μm2 EHI pixels, 10b supply-boosted SAR-ADC and charge-pump circuits consuming 14.25μW from 1.2V resulting in a lowest power imager with 1.32pW/frame∙pixel.
An 80μvrms-Temporal-Noise 82dB-Dynamic-Range CMOS Image Sensor with a 13-to-19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC
M-W. Seo, S. Suh, T. Iida, H. Watanabe, T. Takasawa, T. Akahori, K. Isobe,
T. Watanabe, S. Itoh, S. Kawahito
Shizuoka University, Hamamatsu, Japan
Brookman Technology, Hamamatsu, Japan
Sanei Hytechs, Hamamatsu, Japan
A 1Mpixel, 7.5μm pixel pitch, 0.18μm CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μVrms (1.2e-) temporal noise, 82dB dynamic range using 64 samplings in the folding-integration ADC mode. Variable gray-scale resolution of 13b through 19b is obtained by changing the number of samplings for pixel outputs.
A Sub-Electron Readout Noise CMOS Image Sensor with Pixel-Level Open-Loop Voltage Amplification
C. Lotto, P. Seitz, T. Baechler
Heliotis, Root Längenbold, Switzerland
CSEM, Zurich, Switzerland
CSEM, Landquart, Switzerland
EPFL, Neuchâtel, Switzerland
A 256×256 pixel, 11μm pixel pitch, 0.18μm CMOS image sensor featuring pixel-level open-loop voltage amplification reaches a readout noise of 0.86e- and a dynamic range of 90dB in a single readout using a low-complexity readout circuit with 60fps. A reset method based on negative feedback allows the use of open-loop amplification while achieving PRNU of 2.5% and a peak linearity error of 1.7%.
A 300mm Wafer-Size CMOS Image Sensor with In-Pixel Voltage-Gain Amplifier and Column-Level Differential Readout Circuitry
Y. Yamashita, H. Takahashi, S. Kikuchi, K. Ota, M. Fujita, S. Hirayama, T. Kanou,
S. Hashimoto, G. Momma, S. Inoue
Canon, Kawasaki, Japan
A 1.6Mpixel, 202×205mm2 CMOS image sensor on 300mm wafer consists of pixels of 160μm pitch with a 0-to-24dB variable gain in-pixel voltage amplifier. Reset and integrated signals are simultaneously read out from the pixel through a pair of column lines. It achieves a sensitivity of 25Me-/lux∙s, random noise of 13e-rms and operates at 100fps with global synchronous shutter.
An Angle-Sensitive CMOS Imager for Single-Sensor 3D Photography
A. Wang, P. R. Gill, A. Molnar
Cornell University, Ithaca, NY
A 0.18μm 3D CMOS image sensor composed of angle-sensitive pixels captures both local incident angle and intensity. The 400×384 pixel array has a 7.5μm pitch and local diffraction gratings over each pixel. One such chip, using one lens and ambient light, enables post-capture refocus and range finding accurate to ±1.3cm at 50cm.
A 1/13-inch 30fps VGA SOC CMOS mage Sensor with Shared Reset and Transfer-Gate Pixel Control
R. Johansson, A. Storm, C. Stephansen, S. Eikedal, T. Willassen, S. Skaug, T. Martinussen, T. Whittlesea, G. Ali, J. Ladd, X. Li, S. Johnson, V. Rajasekaran, Y. Lee, J. Bai, M. Flores, G. Davies, H. Samiy, A. Hanvey, D. Perks
Aptina Imaging, Oslo, Norway
Aptina Imaging, Bracknell, United Kingdom
Aptina Imaging, San Jose, CA
Aptina Imaging, Corvallis, OR
This paper describes a 1/13-inch VGA SoC CMOS image sensor, with a 1.75μm pixel pitch capable of outputting 30fps at full resolution. The paper focuses on the sensor core, with a size of 1.77mm2 and a power consumption of 17mW. Thel pixel architecture uses a pixel-sharing scheme that improves low-light performance.
A 1/2.33-inch 14.6M 1.4μm-pixel Backside-Illuminated CMOS Image Sensor with Floating Diffusion Boosting
S. Lee, K. Lee, J. Park, H. Han, Y. Park, T. Jung, Y. Jang, B. Kim, Y. Kim, S. Hamami, U. Hizi, M. Bahar, C. Moon, J. Ahn, D. Lee, H. Goto, Y-T. Lee
Samsung Electronics, Yong-In, Korea
Samsung Semiconductor, Ramat-Gan, Israel
A 1/2.33-inch 14.6Mpixel CIS is developed by employing a 1.4μm BSI pixel with a floating diffusion boosting scheme driven by coupling with additional row-wise metal-line, achieving 30% higher QE than that of an FSI sensor, 87lux for SNR=10, and no image lag, for high-sensitivity and high-speed applications.
An APS-C Format 14b Digital CMOS Image Sensor with a Dynamic Response Pixel
D. Pates, J-H. Lyu, S. Osawa, I. Takayanagi, T. Sato, T. Bales, K. Kawamura, E. Pages, S. Matsuo, T. Kawaguchi, T. Sugiki, N. Yoshimura, J. Nakamura, J. Ladd, Z. Yin, R. Iimura, X. Fan, S. Johnson, A. Rayankula, R. Mauritzson, G. Agranov
Aptina Imaging, San Jose, CA
Aptina Imaging, Tokyo, Japan
Aptina Imaging, Bracknell, United Kingdom
A 16M APS-C format CMOS image sensor with 14b SAR-ADC and 8-lane LVDS output is fabricated and characterized. A 4.78μm dynamic response pixel with ring gate transistors and no STI provides 62% QE, responsivity of 49.5ke-/lux∙s, and dark current of 17e-/s @ 60°C. The readout noise floor is 2.2e- with column FPN of 0.11e- in HCG mode.
A 17.7Mpixel 120fps CMOS Image Sensor with 34.8Gb/s Readout
T. Toyama, K. Mishina, H. Tsuchiya, T. Ichikawa, H. Iwaki, Y. Gendai, H. Murakami, K. Takamiya, H. Shiroshita, Y. Muramatsu, T. Furusawa
Sony, Kanagawa, Japan
Sony LSI Design, Kanagawa, Japan
A 17.7Mpixel CMOS image sensor with a 27.5mm optical format realizes 120fps at 12b using 90nm CMOS. This sensor achieves 2.75e-rms random noise at 12b, 120fps with a maximum data rate of 34.8Gb/s. The 16 channels of scalable low-voltage signaling I/F with embedded clock operate at 2.376Gb/s each and the single-slope ADC ramp generator runs at 2.376GHz.
A 160×128 Single-Photon Image Sensor with On-Pixel 55ps 10b Time-to-Digital Converter
C. Veerappan, J. Richardson, R. Walker, D-U. Li, M. W. Fishburn, Y. Maruyama, D. Stoppa, F. Borghetti, M. Gersbach, R. K. Henderson, E. Charbon1
Delft University of Technology, Delft, The Netherlands
STMicroelectronics, Edinburgh, United Kingdom
University of Edinburgh, Edinburgh, United Kingdom
Fondazione Bruno Kessler - IRST, Trento, Italy
EPFL, Lausanne, Switzerland
A 160×128 pixel array is presented detecting photons with 55ps time resolution. Each pixel comprises a counter, a time-to-digital converter, and a 10b memory, while a frame is read out every 20μs. The sensor is well suited for applications such as fast fluorescence lifetime imaging, optical rangefinding, and time-correlated single-photon counting.
A 1.32pw/frame∙pixel 1.2v CMOS Energy-Harvesting and Imaging (EHI) APS Imager
S. U. Ay
University of Idaho, Moscow, ID
A CMOS energy-harvesting and imaging (EHI) APS imager capable of 7.4fps video capture and 3.5μW power generation is designed, fabricated, and tested in 0.5μm CMOS. It has a 54×50 array of 21μm2 EHI pixels, 10b supply-boosted SAR-ADC and charge-pump circuits consuming 14.25μW from 1.2V resulting in a lowest power imager with 1.32pW/frame∙pixel.
An 80μvrms-Temporal-Noise 82dB-Dynamic-Range CMOS Image Sensor with a 13-to-19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC
M-W. Seo, S. Suh, T. Iida, H. Watanabe, T. Takasawa, T. Akahori, K. Isobe,
T. Watanabe, S. Itoh, S. Kawahito
Shizuoka University, Hamamatsu, Japan
Brookman Technology, Hamamatsu, Japan
Sanei Hytechs, Hamamatsu, Japan
A 1Mpixel, 7.5μm pixel pitch, 0.18μm CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μVrms (1.2e-) temporal noise, 82dB dynamic range using 64 samplings in the folding-integration ADC mode. Variable gray-scale resolution of 13b through 19b is obtained by changing the number of samplings for pixel outputs.
A Sub-Electron Readout Noise CMOS Image Sensor with Pixel-Level Open-Loop Voltage Amplification
C. Lotto, P. Seitz, T. Baechler
Heliotis, Root Längenbold, Switzerland
CSEM, Zurich, Switzerland
CSEM, Landquart, Switzerland
EPFL, Neuchâtel, Switzerland
A 256×256 pixel, 11μm pixel pitch, 0.18μm CMOS image sensor featuring pixel-level open-loop voltage amplification reaches a readout noise of 0.86e- and a dynamic range of 90dB in a single readout using a low-complexity readout circuit with 60fps. A reset method based on negative feedback allows the use of open-loop amplification while achieving PRNU of 2.5% and a peak linearity error of 1.7%.
A 300mm Wafer-Size CMOS Image Sensor with In-Pixel Voltage-Gain Amplifier and Column-Level Differential Readout Circuitry
Y. Yamashita, H. Takahashi, S. Kikuchi, K. Ota, M. Fujita, S. Hirayama, T. Kanou,
S. Hashimoto, G. Momma, S. Inoue
Canon, Kawasaki, Japan
A 1.6Mpixel, 202×205mm2 CMOS image sensor on 300mm wafer consists of pixels of 160μm pitch with a 0-to-24dB variable gain in-pixel voltage amplifier. Reset and integrated signals are simultaneously read out from the pixel through a pair of column lines. It achieves a sensitivity of 25Me-/lux∙s, random noise of 13e-rms and operates at 100fps with global synchronous shutter.
An Angle-Sensitive CMOS Imager for Single-Sensor 3D Photography
A. Wang, P. R. Gill, A. Molnar
Cornell University, Ithaca, NY
A 0.18μm 3D CMOS image sensor composed of angle-sensitive pixels captures both local incident angle and intensity. The 400×384 pixel array has a 7.5μm pitch and local diffraction gratings over each pixel. One such chip, using one lens and ambient light, enables post-capture refocus and range finding accurate to ±1.3cm at 50cm.
A 1/13-inch 30fps VGA SOC CMOS mage Sensor with Shared Reset and Transfer-Gate Pixel Control
R. Johansson, A. Storm, C. Stephansen, S. Eikedal, T. Willassen, S. Skaug, T. Martinussen, T. Whittlesea, G. Ali, J. Ladd, X. Li, S. Johnson, V. Rajasekaran, Y. Lee, J. Bai, M. Flores, G. Davies, H. Samiy, A. Hanvey, D. Perks
Aptina Imaging, Oslo, Norway
Aptina Imaging, Bracknell, United Kingdom
Aptina Imaging, San Jose, CA
Aptina Imaging, Corvallis, OR
This paper describes a 1/13-inch VGA SoC CMOS image sensor, with a 1.75μm pixel pitch capable of outputting 30fps at full resolution. The paper focuses on the sensor core, with a size of 1.77mm2 and a power consumption of 17mW. Thel pixel architecture uses a pixel-sharing scheme that improves low-light performance.
A 1/2.33-inch 14.6M 1.4μm-pixel Backside-Illuminated CMOS Image Sensor with Floating Diffusion Boosting
S. Lee, K. Lee, J. Park, H. Han, Y. Park, T. Jung, Y. Jang, B. Kim, Y. Kim, S. Hamami, U. Hizi, M. Bahar, C. Moon, J. Ahn, D. Lee, H. Goto, Y-T. Lee
Samsung Electronics, Yong-In, Korea
Samsung Semiconductor, Ramat-Gan, Israel
A 1/2.33-inch 14.6Mpixel CIS is developed by employing a 1.4μm BSI pixel with a floating diffusion boosting scheme driven by coupling with additional row-wise metal-line, achieving 30% higher QE than that of an FSI sensor, 87lux for SNR=10, and no image lag, for high-sensitivity and high-speed applications.
An APS-C Format 14b Digital CMOS Image Sensor with a Dynamic Response Pixel
D. Pates, J-H. Lyu, S. Osawa, I. Takayanagi, T. Sato, T. Bales, K. Kawamura, E. Pages, S. Matsuo, T. Kawaguchi, T. Sugiki, N. Yoshimura, J. Nakamura, J. Ladd, Z. Yin, R. Iimura, X. Fan, S. Johnson, A. Rayankula, R. Mauritzson, G. Agranov
Aptina Imaging, San Jose, CA
Aptina Imaging, Tokyo, Japan
Aptina Imaging, Bracknell, United Kingdom
A 16M APS-C format CMOS image sensor with 14b SAR-ADC and 8-lane LVDS output is fabricated and characterized. A 4.78μm dynamic response pixel with ring gate transistors and no STI provides 62% QE, responsivity of 49.5ke-/lux∙s, and dark current of 17e-/s @ 60°C. The readout noise floor is 2.2e- with column FPN of 0.11e- in HCG mode.
A 17.7Mpixel 120fps CMOS Image Sensor with 34.8Gb/s Readout
T. Toyama, K. Mishina, H. Tsuchiya, T. Ichikawa, H. Iwaki, Y. Gendai, H. Murakami, K. Takamiya, H. Shiroshita, Y. Muramatsu, T. Furusawa
Sony, Kanagawa, Japan
Sony LSI Design, Kanagawa, Japan
A 17.7Mpixel CMOS image sensor with a 27.5mm optical format realizes 120fps at 12b using 90nm CMOS. This sensor achieves 2.75e-rms random noise at 12b, 120fps with a maximum data rate of 34.8Gb/s. The 16 channels of scalable low-voltage signaling I/F with embedded clock operate at 2.376Gb/s each and the single-slope ADC ramp generator runs at 2.376GHz.
A 160×128 Single-Photon Image Sensor with On-Pixel 55ps 10b Time-to-Digital Converter
C. Veerappan, J. Richardson, R. Walker, D-U. Li, M. W. Fishburn, Y. Maruyama, D. Stoppa, F. Borghetti, M. Gersbach, R. K. Henderson, E. Charbon1
Delft University of Technology, Delft, The Netherlands
STMicroelectronics, Edinburgh, United Kingdom
University of Edinburgh, Edinburgh, United Kingdom
Fondazione Bruno Kessler - IRST, Trento, Italy
EPFL, Lausanne, Switzerland
A 160×128 pixel array is presented detecting photons with 55ps time resolution. Each pixel comprises a counter, a time-to-digital converter, and a 10b memory, while a frame is read out every 20μs. The sensor is well suited for applications such as fast fluorescence lifetime imaging, optical rangefinding, and time-correlated single-photon counting.
ISSCC 2011 Abstracts Published
![ISSCC 2011 Abstracts Published]()
Reviewed by MCH
on
November 22, 2010
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