Caeleste published two new papers presented at the CNES CMOS Detector Workshop held on Dec 8-9 in Toulouse.
The first presentation covers e2v and Caeleste collaborative work on high-speed BSI sensor with large 24um 4T pixels. The sensor is manufactured by Tower in 0.18um process. The final product array size is 1680x1680 and it can be read out at 1000fps speed. The article talks about a smaller size prototype. 5.5um thick BSI substrate allows 90-95% peak QE.
The second presentation describes SensL, Caeleste and Vrije University of Brussels work on high speed SPAD photon counting array suitable for ToF sensing. The hybrid imager resolution is 128x2. The pixel size is 100x100um. With a nice analog time interpolation the sensor was able to achieve 154ps RMS time resolution or a little worse than 2cm range resolution. Each pixel has 479(!) transistors, including 15-bit time counter:
The first presentation covers e2v and Caeleste collaborative work on high-speed BSI sensor with large 24um 4T pixels. The sensor is manufactured by Tower in 0.18um process. The final product array size is 1680x1680 and it can be read out at 1000fps speed. The article talks about a smaller size prototype. 5.5um thick BSI substrate allows 90-95% peak QE.
The second presentation describes SensL, Caeleste and Vrije University of Brussels work on high speed SPAD photon counting array suitable for ToF sensing. The hybrid imager resolution is 128x2. The pixel size is 100x100um. With a nice analog time interpolation the sensor was able to achieve 154ps RMS time resolution or a little worse than 2cm range resolution. Each pixel has 479(!) transistors, including 15-bit time counter:
Caeleste, e2v, SensL Papers at CNES CMOS Detector Workship 2009
Reviewed by MCH
on
December 23, 2009
Rating:
Reviewed by MCH
on
December 23, 2009
Rating:
No comments: